The invention relates to an output driver circuit in which the generation of electromagnetic interference at high switching speeds is substantially reduced. The circuit comprises two capacitors which are connected in negative feedback between the output node and the gates of the output transistors, with the result that the edge steepness of the output signal is reduced. From the prior art various solutions are known to solve the problems encountered in output circuits in the case of high switching speeds.
EP-A 0 368 524 describes an output driver circuit in which capacitors are also connected between the output and the gates of the output transistors in order to reduce the switching speed of the output transistors, and hence to reduce the voltage peak in the supply voltage and in the ground lead.
EP-A-0 379 881 describes an output driver circuit in which a single capacitor is connected between the output node and the gate of a lower output transistor in order to impart a specific shape to the voltage on the gate of this output transistor.
In the former document, the capacitors serve to reduce the steepness of the output signal transitions in conjunction with the two resistors and the inverter inserted in the path of the input signal. These steps lead to an unacceptable delay and, moreover, the output signal edges cannot be suitably defined. The circuit disclosed in the second document also suffers from excessive delay, even though therein the output signal edges can be more accurately defined as a result of the operation of the lower transistor with an operating voltage which varies as a square root of time.
None of the prior art documents discloses the characteristics of a suitably defined, controllable edge steepness in combination with acceleration circuits for accelerating the start of the transition.
DE 42 06 864 describes an output driver circuit intended to achieve a reduced edge steepness of the output signal without using capacitors. For each output transistor in this circuit there is provided a driver circuit which comprises an inverter and a delay circuit connected to the inverter. In the event of signal transition on the input, intended to turn over the output transistor, the charge of the gate of the output transistor is quickly reversed, via the low-resistance inverter, until the output transistor starts to conduct. At that instant the inverter should be switched to the high-resistance state by the delay circuit, so that the gate of the output transistor change its level only slowly and slowly turns on the output transistor. However, this necessitates accurate adjustment of various parameters, including the delay time of the delay circuit, which adjustment is difficult to realize.